When you purchase through links on our articles, Future and its syndication partners may earn a commission.

SRAM Scaling stopped suddenly with the latest round of new process nodes, portending a bleak future where on-chip memories become more and more expensive. However, unlike what we have seen in the pastSRAM scaling apparently isn’t dead after all.

TSMC announced that its N2 process technology (2nm class) delivers substantial improvements in performance, power efficiency, and area (PPA) over previous generation nodes. However, there is one more thing that TSMC has not yet publicly discussed: significantly smaller SRAM cells and higher SRAM density (38 MB/mm^2), which will impact cost and performance next-generation processors and GPUs. and systems on chips.

TSMC’s upcoming L2 node will debut with global gate (GAA) nanosheet transistors, promising a significant reduction in power and an increase in transistor performance and density. Compared to N3E manufacturing technology, chips built on N2 are expected to reduce power consumption by 25-30% (at equivalent number and frequency of transistors), improve performance by 10-15% (with the same number of transistors and the same power), and obtain a 15% increase in transistor density (while maintaining the same speed and power).

But a notable aspect of TSMC’s N2 is that this production node also reduces the size of HD SRAM bit cells to approximately 0.0175 µm^2 (enabling 38 Mb/mm^2 SRAM density), from 0.021 µm^2 in the case of N3 and N5, according to a article that TSMC will present at the next IEDM conference in December.

This is a major step forward as SRAM has become particularly difficult to upgrade in recent years. For example, TSMC’s N3B (1st generation 3nm class technology) offers little advantage over the N5 (a 5nm class node) in this regard, while the N3E’s HD SRAM bit cell size ( 2nd generation 3nm process) is 0.021 µm^2 and offers no SRAM scaling advantage over N5. With N2, TSMC finally succeeded in reducing the size of HD SRAM bit cells and, therefore, increasing the SRAM density.

TSMC’s GAA nanosheet transistors appear to be the main factor in reducing the size of HD SRAM bit cells. GAA transistors provide enhanced electrostatic control over the channel by completely surrounding it with gate material, which helps reduce leakage and allows the transistors to shrink in size while maintaining performance. This allows for better scaling of transistor dimensions, which is crucial for reducing the size of individual components such as SRAM cells. In addition, GAA structures allow more precise adjustment of the threshold voltage, which is essential for the reliable operation of transistors in general, and SRAM cells in particular, allowing their size to be further reduced.

Modern CPU, GPU, and SoC designs are very SRAM-intensive, as these processors rely heavily on SRAM for many caches to efficiently handle large amounts of data. Accessing data from memory is both performance-intensive and power-intensive, making sufficient SRAM crucial for optimal performance. In the future, the demand for caches and SRAM is expected to continue to grow, so TSMC’s achievement in SRAM cell sizing represents a very important breakthrough.

Earlier this year, TSMC said that N2 gate nanosheet transistors delivered more than 90% of their target performance and that yields of 256MB (32MB) SRAM devices exceeded 80% in some batches. As of March 2024, the average efficiency of 256 MB SRAM has reached around 70%, up significantly from around 35% in April 2023. Device performance has also shown steady improvement, with higher frequencies obtained without increasing energy consumption.