By Agnisys

Introduction

In today’s rapidly evolving semiconductor industry, system-on-chip (SoC) designers face significant challenges when integrating thousands of IP blocks from various vendors, often presented in different formats. Manually assembling and debugging these components can lead to quality issues, extended time-to-market (TTM) and complex integration hurdles. As designs become more complex, the need to validate connectivity and compliance with IP-XACT standards becomes increasingly critical.

Presentation of IDS-Integrate

IDS-Integrate is designed to address these challenges by automating the assembly and packaging of numerous IP blocks, including third-party options, into cohesive SoC designs. This powerful tool simplifies the process of integrating IP-XACT (IEEE 1685-2009, 2014 and 2022) and RTL (Verilog, SystemVerilog) formats, allowing designers to automatically generate high-quality outputs such as RTL, IP-files XACT, documentation. , assertions, graphical views and C/C++ headers.

The versatile Tcl and Python APIs facilitate connectivity specifications, enabling automatic connections between initiators, targets, drivers, receivers, clocks, resets, and ports, as well as the ability to use regular expressions. It also supports features like partitioning and hierarchy flattening, enabling seamless restructuring of components from one project to another. Built-in design rule checks validate connectivity before generating results, ensuring compliance and reliability throughout the SoC design process.

Challenges and use cases of automated chip assembly

Manually connecting hundreds or thousands of blocks in a high-level SoC design is a tedious and error-prone task. Designers often struggle to connect signals with similar names, where typographical errors are almost inevitable. The repetitive process of connecting multiple instantiations of the same block can be particularly frustrating. Typically, interconnect errors are detected late in the project, only when full chip simulation is underway, making debugging difficult due to the complexity of the design.

Agnisys addresses these challenges with IDS-Integrate, applying specification automation to assembly and interconnection at the SoC level. This tool provides a flexible and customizable environment tailored to meet the specific design requirements of complete chips.

IDS-Integrate empowers designers by enabling use cases such as:

• Connect the blocks generated by the tool with your design blocks and create a wrapper around them
• Read an IP-XACT component and connect it to existing blocks
• Connect an AHB bus with an APB slave by automatically instantiating a bridge
• Connecting multiple AHB blocks to an AHB master via automatic aggregator instantiation
• Move a block from a deep hierarchy several levels higher
• Generating SystemVerilog Assertions (SVA) for Connectivity Controls Using Formal Verification

With these features, IDS-Integrate improves development processes, ensuring high-quality designs while significantly reducing manual efforts.

Features and Benefits

By automating the generation of integrated outputs, the tool eliminates manual coding errors and automates integration. Connectivity is validated through built-in design rule checks and assertions, ensuring all components work together seamlessly.

The tool supports assembling SoC designs with both custom IP blocks and commercial offerings. The automatically generated RTL includes timing logic for the clock domain crossovers (CDCs) needed to connect the IP to internal and external buses, as well as any required bus bridges, aggregators, or multiplexers.

In addition, IDS-Integrate allows efficient management of block instance tables thanks to RTL and IP-XACT specifications parameterized via the Tcl/Python APIs. It integrates the TGI (Tight Generator Interface) API, improving integration capabilities with third-party extensions. Latest features include support for power specifications in Unified Power Format (UPF), Standard Design Constraints (SDC), CDC specifications and advanced Semantic Consistency Rules (SCR) for IP-XACT, which positions IDS- Integrate as a cutting-edge solution. . The addition of spreadsheet-based connectivity specifications further streamlines the design process, improving overall productivity and driving innovation in SoC projects.

The role of IP-XACT and IDS-Integrate

IDS-Integrate plays a central role in streamlining the SoC design process. By automating the assembly, packaging and catalog generation of numerous IP blocks, it allows designers to automatically generate high-quality results and ensure efficient component restructuring. The tool supports automatic connection of various elements while validating connectivity to ensure compliance and reliability.

Conclusion

In conclusion, adopting IP-XACT and leveraging IDS-Integrate can significantly shorten the SoC development cycle. By standardizing data exchange and automating critical processes, teams can streamline workflows, improve collaboration, and accelerate their SoC designs to market. This approach not only improves efficiency, but also improves the quality and reliability of the final product, paving the way for innovation in the semiconductor industry.